Field of the Disclosure
The present disclosure generally relates to pipelined instruction execution in a processing device and, more particularly, to register file management during pipelined instruction execution.
Description of the Related Art
Register renaming often is used in pipelined processor architectures so as to dynamically map architected registers to a set of physical registers. As only a subset of architected registers are in use by the processor at any given time, register renaming typically allows the architected register set to be represented by a smaller set of physical registers, thereby saving the power and area that otherwise would be needed for a one-to-one mapping between physical registers and architected registers. However, in certain circumstances, there may be more architected registers in use in a processor than there are physical registers in the processor, thereby requiring the processor to stall until one or more physical registers are released for mapping to unmapped architected registers.